Yeh! 450mm 的時代即將來臨了。
猶記得去年Applied Materials Brooks Automation Intel 等大廠來台舉辦有關300mm Prime的研討會，會中有人提問：設備廠商如Applied Materials 是否會朝向450mm的趨勢邁進，Applied Materials 的回答語帶保留地說，450mm 的設備研發龐大，目前在市場的規模尚未明朗之前，基本上Applied Materials 是不會冒進，反而鼓勵Fab廠商，以加強機台設備的Efficiency，提高生產力的300mm Prime為目標。然而，Chip Maker的龍頭Intel 已然建立首座的450mm Fab廠，而韓國的Samsung 與台灣的TSMC 也積極地透入，要求設備廠商提供解決方案。暫且不估算450mm的設備投資有多大，有了買家之後，且這趨勢將無法避免，各設備廠商當然會暗中較勁，而台面 上卻嚷嚷450mm還不到時候。 但由Sematech近來對450mm 的Test Bed測試來看，450mm 已不再是搖不可及的目標，只是在2012年以前所有的設備廠商能否能到位(Ready)，這目標會比較有爭議。
當初主要的設備廠商極力推薦300mm Prime的主要目的在於致力改善OEE (Overall Effecitiveness & Efficiency)。他們宣稱300mm的Fab廠的稼動率並沒有發揮極致，有很大的改善空間。事實也的確如此。但，問題在於OEE的改善需要Fab 廠與設備廠商兩者互相配合，才能有改善的成效。然而，現實環境裡設備廠商不是晶圓的製造者，所以無法真切感受到Fab廠的痛處。例如：Fab廠的 Stocker一直為人詬病，因為其無法確實掌握Carrier的動態。再者，RTD已被300mm列入必備控管Carrier移動管理的利器，然而 Rule Based的規則建立，需長時間的觀察學習，致Carrier的運載管理的效能打了折扣。 依我的看法，與其將力氣花在提升機台稼動率的改善，來提升良率，到不如直接跳入450mm的行列，運用產能的擴張，來改善良率的不足，之後再去Tune機 台的稼動率來的實際。之所以會有這種建議，是來自於: (1) 450mm 是個無可避免的趨勢，Fab廠除非自願提早下車，否則還是趕緊加入。(2) 將良率提升由70%至80%，與80%提升至90%兩者所投入的人力資源是無法相比的，後者更可能受限於環境技術等因素，所以用傳統的思維去考量，用高昂 的機台設備去量產，縱然良率相同，但是產出卻是驚人的。在Time to Market的時代，時間就是金錢，切莫等到機台良率都達到完備了，再想到市場的需求，這時為時已晚了。
參考
http://www.eetasia.com/ARTP_8800534242_480200.HTM
Sematech: 450mm program is on track
Posted: 14 Jul 2008
International Sematech is moving full speed ahead with its 450mm programs, but the question is whether the industry can meet its lofty goals in building 450mm fabs by 2012.
On July 9, chipmaking consortium Sematech provided an update on its next-generation 300- and 450mm programs, saying that they are on track and making steady progress.
The consortium is up and running with its "factory integration test bed" facility for the development of 450mm fab tools. Sematech is also testing silicon wafers based on 450mm technology. And the group claims it has made progress on its so-called "Next Generation Factory" (NGF) program, geared to bring lower costs and reduced cycle times in 300mm wafer manufacturing.
Recently, Sematech unveiled two next-generation fab programs: 300mmPrime and the International Sematech Manufacturing Initiative's ISMI 450mm effort.
Need for 450mm?
There is widespread support among the fab-tool community for 300mmPrime, which looks to boost the efficiency of existing 300mm fabs, thereby pushing out the need for 450mm plants.
The newer, more controversial ISMI 450mm program, announced last year at Semicon West, calls for some chipmakers to make a more direct transition from 300mm to the larger 450mm wafer size.
Many fab-tool vendors are reluctant to endorse the next-generation wafer size or devise 450mm tools, saying that it is simply too expensive. Many vendors claim that 300mm fabs are suitable for most applications and the real goal for the industry is to improve the productivity of current plants.
"There is still a lot of concern and debate" about 450mm fabs among the equipment makers, said Scott Kramer, VP of manufacturing at International Sematech, but "the tide has shifted over the last 12 months."
A few fab-tool and materials vendors have develop 450mm technologies, but many suppliers have publically slammed Sematech's 450mm program, saying the economics simply don't add up.
However, the mood is somewhat beginning to change, especially when Intel Corp., Samsung Electronics and Taiwan Semiconductor Manufacturing Co. Ltd in May reached an agreement on the need for industry collaboration for 450mm wafers starting in 2012. Intel, Samsung and TSMC indicate that the semiconductor industry can improve its return on investment and reduce 450mm research and development costs by applying aligned standards, rationalizing changes from 300mm infrastructure and automation, and working toward a common timeline.
Intel, Samsung and TSMC represent a major chuck of the world's capital equipment buyers. Because those companies are pushing for 450mm fabs, it could jumpstart the development of the next-generation wafer size.
Many believe that 450mm tools will not be ready in the 2012 timeframe. Even Kramer acknowledged that the 2012 timetable for 450mm fabs is "very aggressive."
"Those are risky goals," he said.
300mm vs. 450mm
To jumpstart the 450mm era, Sematech last year announced a plan to devise a "factory integration test bed" facility for the development of 450mm fab tools. The proposed facility would help enable chip-equipment makers to develop the initial fab-automation gear, such as carriers, load ports, modules and other items.
Providing an update on the "test bed," Tom Abell, 450mm program manager at Sematech, said the facility is operational. At present, Sematech has put the "test bed" at the Advanced Technology Development Facility, the consortium's former R&D foundry. Based in Austin, Texas, that facility was recently sold to SVTC Technologies Inc.
The facility is using the first 450mm handlers from Brooks Automation Inc. and carriers from Entegris Inc. The pitch specification for these tools is 10mm. With the fab-automation gear, Sematech has demonstrated a 450mm wafer running at 100,000 cycles, Abell said.
Sematech is also in the process of developing a standard for 450mm silicon wafers. At present, there are five wafer-thickness standards vying for dominance in the arena, each with their own set of "tradeoffs," Kramer said.
Initially, Sematech is exploring 450mm wafers with an overall thickness of 925-micron. Last year, Japan's Nippon Mining & Metals Co. Ltd claimed to have developed the first 450mm polycrystalline silicon wafers. Sematech is testing wafers from Nippon Mining, but the consortium is also talking to other silicon wafer suppliers, Kramer said.
NFG Program
The consortium also claims it has made progress on its 300mm NGF Program, which focuses on global infrastructure for 300mm hardware and software. It includes 300mmPrime and is supported by ISMI's four other programs in continuous improvement, 450mm manufacturing, metrology, and environment, safety and health.
"The 300mm NGF Program offers a wider look at 300mm productivity with a broader set of initiatives—and it works for companies whose business plans don't necessarily include a larger wafer size," said Kramer in a statement last year. "Our priority is to extend productivity improvements to existing 300mm fabs in addition to supporting 'green field' facilities."
The overall goal of the program is to reach a 30 percent reduction in cost per wafer, and a 50 percent reduction in cycle time. Like last year, Sematech said it has not been able to reach those targets.
In new simulation data, the consortium claims it is coming closer to its goals. It has simulated a 30- to 40 percent boost in cycle times and 10 to-15 percent improvements in cost. In other data, it has demonstrated a 60 percent boost in cycle times and a 10 percent improvement in cost.
The bottleneck remains in moving the wafer lots from one tool to another. The goal is to process wafers without any delays, according to Sematech.
- Mark LaPedus
EE Times
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